The present invention relates to a single-chip microcomputer for controlling peripheral circuits such as memories or dual port memories.
Japanese Patent Application Kokai No. 61-141,064 discloses that when a single-chip microcomputer of relatively high process speed accesses a peripheral circuit such as a read only memory (ROM) or random access memory (RAM), or a dual port memory, a wait time setting control circuit is added to the single-chip microcomputer to divide the frequency of a clock signal outputted from the microcomputer for permitting access with a clock signal of lower frequency. The wait time setting control circuit and address decoder must be made from a general purpose large scale integrated circuit, resulting in the increased mounting area.